Technical Field
The present invention relates generally to the field of testing memory arrays, and more particularly to testing memory arrays with ECC circuitry.
In general, in the fabrication of integrated circuits it is important to test the circuits once fabricated to assure they meet the requisite quality and reliability targets for the targeted product application. In memory technologies (be they dynamic random access memories (DRAM); static RAM; or embedded RAM) it is particularly important to conduct these tests so as to identify and replace faulty storage cells, such that the memory can still meet the product application.
Such memories are regular structures which have well defined test pattern sets. By “regular,” we mean that a memory array typically has a repeating topology and sequence of transistors and other structures, such that failure mechanisms tend to affect the device in relatively uniform ways, and tend to accurately follow well-established fault models. Normally such test patterns are provided by a test machine that provides both the test patterns and the associated addresses to the address and data I/O of the device under test. Alternatively, a built-in self-test (BIST) macro can be employed that provides such patterns internally. U.S. Pat. No. 6,205,564 B1, “Optimized Built-In Self-Test Method and Apparatus for Random Access Memories” discusses the use of March bit test pattern tests with BIST. A particular embodiment of BIST is discussed in U.S. Pat. No. 5,535,164, “BIST Tester for Multiple Memories,” assigned to the assignee of the present invention.
Error correction codes (ECC) such as the well-known Hamming codes for double error detect, single error correct (DED/SEC) are used in higher-end memory systems to correct single bit failures (soft errors) arising from isolated events such as extraneous alpha particle radiation. Memory systems have been proposed that carry out ECC at the chip level. See for example U.S. Pat. No. 4,335,459, “Single Chip Random Access Memory With Increased Yield and Reliability,” and U.S. Pat. No. 5,134,616, “Dynamic RAM with On-Chip ECC and Optimized Bit and Word Redundancy,” assigned to the assignee of the present invention.
In the past, ECC has been used primarily to correct soft errors (that is, errors that cause a particular bit to fail on a particular occasion) versus hard errors (the memory cell itself is faulty). The latter errors have been corrected by redundancy. Thus, when both ECC and redundancy have been used on a memory product, the typical procedure has been to first test the array and use redundancy to fix hard errors, then using ECC to address soft errors.
However, when single bit Error Correction Code (ECC) is used to repair hard or stuck failures, as opposed to fixing soft failures due to alpha particles or cosmic rays, a different redundancy calculation must be employed from that typically used. Normally when row redundancy is employed, if a failure is seen then a good redundant row is substituted in its place. It doesn't matter whether there is a single cell fail or a full word line fail. See U.S. Pat. No. 6,026,505.
When ECC is on a memory, a single cell fail (SCF) need not be replaced by a redundant row. The ECC alone will provide SCF tolerance. Any multiple cell failure (MCF) must be replaced by a redundant row. If there is a single cell hard fail, however, and there are extra redundant elements left over after all multibit failures have been replaced, then it is desirous that the single cell failure be replaced by a redundant element.
A need has developed in the art for a more sophisticated memory fault correction system that optimizes the use of both ECC and redundancy to correct for failing bits.